Field of the Invention
Embodiments of the invention generally relate to processes for forming group III/V materials on a silicon substrate using a group III nucleation layer.
Description of the Related Art
Group III/V semiconductors have significant potential as useful materials in high-temperature, high frequency and high power microelectronics and ultra-violet/blue/green optoelectronics by virtue of their wide bandgaps, high thermal conductivities and large electrical breakdown fields. Microelectronic device applications include AlGaNGaN multilayer-based laser diodes, high electron mobility transistors (HEMTs), field effect transistors (FETs), heterojunction bipolar transistors (HBTs), light emitting diodes (LEDs) and ultra-violet photodetectors, as well as (Al,In,Ga) N-based devices generally, including devices for high-frequency, high-power communications, for high-density optical storage, full-color displays, and for other wide bandgap semiconductor applications.
Further, surface layers capable of achieving the performance advantages of group III/V materials may host a variety of high performance electronic devices such as CMOS and quantum well (QW) transistors fabricated from extreme high mobility materials such as, but not limited to, indium antimonide (InSb) and indium arsenide (InAs). Optical devices such as lasers, detectors and photovoltaics may also be fabricated from various other direct band gap materials, such as, but not limited to, gallium arsenide (GaAs) and indium gallium arsenide (InGaAs).
Despite the advantages and utility of such layers, the growth of group III/V materials on silicon substrates presents many challenges. Crystal defects can be generated by lattice mismatch, polar-on-nonpolar mismatch and thermal mismatch between the group III/V semiconductor epitaxial layer and the silicon semiconductor substrate. When the lattice mismatch between the epitaxial layer and substrate exceeds a few percent, the strain induced by the mismatch becomes too great and defects are generated in the epitaxial layer when the epitaxial film relaxes.
Once the film thickness is greater than the critical thickness (film is strained below this thickness and relaxed above this thickness), the strain is relaxed by creating misfit dislocations at the film and substrate interface as well as in the epitaxial film. The epitaxial crystal defects are typically in the form of threading dislocations, stacking faults and twins (periodicity breaks where one portion of the lattice is a mirror image of another). Many defects, particularly threading dislocations, tend to propagate into the “device layer” where the semiconductor device is fabricated. Generally, the severity of defect generation correlates to the amount of lattice mismatch between the group III/V semiconductor and the silicon substrate.
Various buffer layers have been used in attempts to relieve the strain induced by the lattice mismatch between the silicon substrate and the group III/V device layer and thereby reduce the detrimental defect density of the III/V layer. However, layer uniformity between different surface orientations of the silicon substrate has remained a constant problem.
A related difficulty to depositing group III/V layers for CMOS features is conformal deposition on silicon substrates. Traditionally, in heteroepitaxy, buffer layers must be grown to be very thick, such as a buffer layer which is 1 or more microns thick, to overcome the mismatch between the layers and create a high quality crystalline film.
As such, the formation of a conformal layer on different crystal orientations requires the deposition of a thick layer to accommodate for above crystal defects which is not optimal for small feature formation in CMOS.
Therefore, there is a general need for a deposition process with a high deposition rate that can deposit group III/V films uniformly over a large substrate or multiple substrates without regard for lattice mismatch, polar-on-nonpolar mismatch or other difficulties. Further, there is a need in the art for an improved deposition method which does not require a thick buffer layer for the growth of group III/V crystalline layers on a silicon substrate.